1. Field of the Invention
The present invention relates to a shift register, and more particularly, to a shift register for use as a scanning-line driving circuit for an image display apparatus or the like, which is formed by field effect transistors of the same conductivity type only.
2. Description of the Background Art
An image display apparatus (hereinafter referred to as a “display apparatus”) such as a liquid crystal display includes a display panel with a plurality of pixels arrayed in a matrix. A gate line (scanning line) is provided for each row of pixels (pixel line) on the display panel, and gate lines are sequentially selected and driven in a cycle of one horizontal period of a display signal, so that a displayed image is updated. As a gate-line driving circuit (scanning-line driving circuit) for sequentially selecting and driving pixel lines, i.e., gate lines, a shift register for performing a shift operation that makes a round in one frame period of a display signal can be used.
To reduce the number of steps in the manufacturing process of a display apparatus, such shift register used as the gate-line driving circuit is preferably formed by field effect transistors of the same conductivity type only. Accordingly, various types of shift registers formed by N- or P-type field effect transistors only and display apparatus containing such shift registers have been proposed (e.g., Soon Young et al., “Highly Stable Integrated Gate Driver Circuit using a-Si TFT with Dual Pull-down Structure” SID 05 DIGEST, pp. 348-351). As a field effect transistor, a metal-oxide-semiconductor (MOS) transistor, a thin film transistor (TFT), or the like is used.
The gate-line driving circuit is formed of a multistage shift register including a plurality of shift registers provided for each pixel line, i.e., each gate line, and connected in cascade (cascade-connected). For ease of description, each of the plurality of shift registers connected in cascade to constitute the multistage shift register will be called “a unit shift register” throughout the present specification.
As shown in FIG. 1 of Japanese Patent Application Laid-Open No. 2004-246358, for example, a typical unit shift register includes, in its output stage, an output pull-up transistor (Q1) connected between an output terminal (GOUT in this document) and a clock terminal (CKV) and an output pull-down transistor (Q2) connected between the output terminal and a reference voltage terminal (VOFF).
In such shift register, the output pull-up transistor turns on and the output pull-down transistor turns off in response to a predetermined input signal (output signal (GOUTN−1) from the immediately preceding stage), and a clock signal input to the clock terminal in this mode is transmitted to the output terminal, and an output signal (GOUTN) is then output. During a period in which the above-mentioned input signal is not input, the output pull-up transistor turns off and the output pull-down transistor turns on, so that the voltage level (hereinafter briefly called “level”) at the output terminal is kept at the L (low) level.
A display apparatus employing amorphous silicon TFTs (a-Si TFTs) as shift registers of a gate-line driving circuit easily achieves large-area display with great productivity, and is widely used as the screen of a notebook PC, a large-screen display apparatus, etc.
However, an a-Si TFT tends to have its threshold voltage shifted in the positive direction when the gate electrode is continuously positive-biased (dc-biased), resulting in degraded driving capability (current-flowing capability). Particularly, in a unit shift register of a gate-line driving circuit, an output pull-down transistor is turned on so as to output an output signal only in a single selected period per frame of an image and to keep the output terminal at the L level in a period other than that period (non-selected period).
In other words, a conventional unit shift register successively carries out an operation of positively biasing the gate of the output pull-down transistor for a time period almost equal to one frame period (about 16 ms). This causes a shift in threshold voltage (Vth shift) to occur in the output pull-down transistor, which gradually degrades its driving capability (that is, the on-state resistance increases). Then, the output pull-down transistor cannot discharge unnecessary charges if supplied to the output terminal resulting from noise or the like, resulting in a malfunction of erroneous activation of gate line in its non-selected period.
To solve the problem, the aforementioned paper by S. Y. Yoon, et al. presents a gate driver circuit in which dual output pull-down transistors are provided in parallel for the output terminal of the unit shift register and are alternately activated/deactivated by each frame.
In the paper by S. Y. Yoon, et al., for example, each unit shift register as shown in FIG. 4(a) is supplied with two types of signals as shown in FIG. 4(b). These two types of signals are each changed in level per frame so as to activate/deactivate the dual output pull-down transistors. Just after the change in level, each node in the circuit of the unit shift register is making a level transition (on the way of level transition), which may unstabilize the operation of the shift register at that time and cause a malfunction (which will be described later in detail).
It has been found that the above-described problem of Vth shift similarly occurs in an organic TFT, not only in a-Si TFT.